/vr/ - Retro Games

>>6998179
I intentionally dumbed down what I'm talking about so your smooth brain can understand it.

Do you want to know why the mister guys can't seem to get their sdram modules working reliably? Why something as simple as pc133 sdram continuously eludes them, and why they had to make special speed testing cores just to make sure their ram boards work? And then a person tries the same core and ram board on a different DE10-nano board, the test fails?
Because they haven't constrained the input DQ lines correctly. And so you get timing violations on input data being read back into the fpga driven by the sdram. The exact amount of violation depends on the way the fitter routes the LE's near the io ring inside the FPGA. This is why some people have crashing SNES cores and other people don't.

As for why sorgelig doesn't know this, I don't know. They have some bullshit constraints SDC in the framework but it's obviously not doing anything for the timing issue. The second issue is they drive the damn sdram over a fucking 0.1" pin header at 140mhz without even using midpoint termination. And I'm not interested in telling them because they get way too butthurt over anyone insulting their precious open source religion.