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>> No.12327604 [View]
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12327604

a question from my digital design book asks:
>(a) Find a minimum two-level NOR gate circuit to implement F1 and F2, using as many common gates as possible
[math]F_1\left(a,b,c,d\right)=\sum m\left(1,2,4,5,6,8,10,12,14\right)[/math]
[math]F_2\left(a,b,c,d\right)=\sum m\left(2,4,6,8,10,11,12,14,15\right)[/math]
>(b) Realize F1 and F2 using a PLA

I'm able to do (a) just fine, but looking at the solutions manual, I have absolutely no clue how they managed to get those "product terms" in the pic that they used for the PLA table, considering the final NOR-NOR expressions are
[math]F_1\left(A,B,C,D\right)=\left(\left(A+B+C+D\right)'+\left(A'+B+D'\right)'+\left(C'+D'\right)'\right)'[/math]
[math]F_2\left(A,B,C,D\right)=\left(\left(A+B+C+D\right)'+\left(A+C'+D'\right)'+\left(C'+D'\right)'\right)'[/math]

what are those product terms? Converting to SoP doesn't give me those terms either (unless I fucked it up)

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