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>> No.11075724 [View]
File: 52 KB, 761x369, dq2.png [View same] [iqdb] [saucenao] [google]
11075724

>>11075692
>>11075697
now, we'll send D to R and not D to S. but we don't want to always write from D, we only want to when the control (the clock) says to. so we need to do an and first.
pretend in this circuit that the not Q line is on, i.e. the RS latch contains a 0 bit. suppose D has been 1 for a few seconds already. we quickly flash the clock on and off. what happens to the thing stored in the latch? follow all the wires and see where it stabilizes. write down the AND and NOR truth tables if you need to. when you get this, it all clicks.
then you can do the same if D is off (so not D is on) and you flash the clock.
notice that reading from the flipflop only happens on the right, and electricity flows in the left end of a logic gate and out the right end. this corresponds to the left end being the control line of a transistor or two (NOT the input line!), and the right end being the output line of the transistors. that way, electricity from the "read" or "Q" side can never go back in and screw with what's stored in our SR latch - and the ANDs make it so that electricity from the input side can never screw with our SR latch unless we let it in with the CLK.
attach 32 of these together and you get a memory register!

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