>>1729887
Thank you.
I love how well documented these old systems are.
>>1729888
It's a homebrew architecture I've been working on to apply the concepts I learned in senior Computer Architecture.
It's a 16-bit load/store architecture with three operand instructions.
Nothing fancy, but it's very simple and clean, I think.
It's not another Ben Eater SAP clone, that's for sure.
>ISRs in ROM do the user ISR some favors before/after calling it like a subroutine
I was planning on it, OS gets the first crack at it, then it passes it to the User.
>sounds like an address bit.
Well, yeah, I guess so, just one that's only set by In/Out.
I didn't really want to have any 'bank' registers in the CPU core, just makes for one more dependency to keep track of in re-entrant code.
I guess I'm not really bothering with any bus timing differences, since I'll just let myself be spoiled and use modern fast SRAM.
>maybe show opcode list, it might be time to Muntz that fucker
Ok, I'd be impressed if you can muntz this much more, it's already pretty dang lean.
Current Opcodes:
Add (Rd = Rx + Ry)
Sub (Rd = Rx - Ry)
LSL (Rd = Rx << Rd)
LSR (Rd = Rx >> Rd)
Inc (Rd = Rx + 1)
Dec (Rd = Rx - 1)
And (Rd = Rx && Ry)
Or (Rd = Rx || Ry)
Xor (Rd = Rx ^ Ry)
Not (Rd = !Rx)
In (Rd = Rx[Ry].io)
Out (Rx[Ry].io = Rd)
Load (Rd = Rx[Ry].mem)
Store (Rx[Ry].mem = Rd)
Compare (T = Rx ? Ry), where ? can be 'less than', 'equal', 'zero', etc
Halt (Halts the system)
Registers:
R0 - K - Constant, normally zero, but immediate values are loaded here
R1-R4 - General Purpose registers
R5 - Stack pointer by convention, otherwise identical to R1-R4
R6 - T - Test register, true if the value in T is not zero
R7 - Program Counter
All instructions may be predicated based on if T is true or false.
On the chopping block are Inc, Dec, In, Out, and Not, which I might replace with add short immediate, load/store w/ short immediate offset