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/diy/ - Do-It-Yourself


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>> No.1615604 [View]
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it's not actually leakage current. it's base current. it's supposed to flow and is essential to transistor action. if you were using n-channel MOSFETs instead of BJTs (which are voltage-mode), you would not be seeing that effect. you'd be seeing a slightly different one where the source voltage is some volt or two above the gate. that's why logic implementations tend to prefer placing the
anyway, as regards voltage levels, what you have now is an open-collector NAND gate. add a pull-up, then negate the negation with an inverter stage with its own pull-up

also interested in network analysis and would like to know this

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