/diy/ - Do It Yourself

>>1279133
Typically, they'll output Vin - Vdropout.

>>1279146
Is your PMOS backwards or just a drafting error?
>R1
I get good results with 100k. Its main concern is pulling charge back off of Q2's gate fairly quickly.
>R4
Q1's drain will be at 0V when Q1 is off and close to the rail voltage when Q1 is on. You want (R6||R4) / ((R6||R4)+R3) to be slightly more than Q2 threshold when Q1 is off at max tolerable output voltage and R6 / (R6+(R3||R4)) to be slightly less than Q2 threshold when Q1 is on at min tolerable output voltage. You may need to adjust R6 and/or R3 to achieve that. See Pic related, voltage source is a triangle 0-100V, to sort of approximate your CT. Left scope is Q2 gate, middle is Q1 gate, right is output.
The turn-on and turn-off aren't as sharp as I expected. You can add a series-cap-and-resistor in parallel with R4 to sharpen the switching action. I used C=3n3 and R=220k and still got a reasonable simulation. You may wish to play with these values when breadboarding, or if your simulator can generate current waveforms.
The circuit can have trouble converging because simulators don't handle positive feedback perfectly well. Try establishing an initial state of off, with the node on the gate of Q1 set to the initial level of Vin. And/or decrease your time step.
Remember, the goal of this circuit is just to reduce input variation to something a higher-quality post-regulator can handle. With values in pic I get something like a 33V max before the second shunt activates.

>>1279184
Mechanic is a brand name, and apparently a fairly reputable one in the east. Who knows whether your Kester is actually Kester, gnomesayin?