/diy/ - Do It Yourself

Verilog / yosys stupid Q:

I have some counter that gets compared with this TICKS parameter
parameter TICKS = 400;

It works, but it's inconvenient. I want to save myself the pain of calculating TICKS, so I try using an expression.

parameter FREQ = 17000;
parameter TICKS = 0.5*(12000000/FREQ);

Calculated doesn't work because TICKS somehow turns signed, and later some comparison fails some yosys validation because of that. I can just force both sides signed and it works:

parameter signed TICKS = 0.5*(12000000/FREQ);
reg signed [31:0] r_COUNTER = 0;

But that's not what I want. I want to get rid of signed. Unfortunately, putting "unsigned" in both ends doesn't work, because unsigned doesn't seem to be a reserved word. I try to force it by casting it via $unsigned() function:

parameter TICKS = $unsigned(0.5*(12000000/FREQ));

But then I get "ERROR: Failed to detect width for parameter \TICKS!", therefore something must be very wrong, but for completeness I try forcing the parameter size:

parameter [31:0] TICKS = $unsigned(0.5*(12000000/FREQ));

And it fails with the same error. Advice?