/diy/ - Do It Yourself

Halp
Can someone explain to me what tHR (Read Data Hold) means in this diagram?
The hold times for outputs (tHW, tHA, tHRW) make sense to me - when the processor starts the next cycle, there will be a small delay during which the old values will stay on the bus. But what does hold time mean for the processor's inputs? Following a read cycle, after the falling edge of Φ2, do peripherals need to keep the value read on the data bus for all of tHR (in addition to tDSU (Read Data Setup) before the falling Φ2)? Or is tHR a upper limit, meaning peripherals need to stop outputting to the data bus within that amount of time? Or what?

Diagram is from http://archive.6502.org/datasheets/mos_65ce02_mpu.pdf (page 9)
Modern version (what I'm actually using) is http://archive.6502.org/datasheets/wdc_w65c02s_may_17_2013.pdf, but I found its timing diagram (page 26) to be utterly incomprehensible