/diy/ - Do It Yourself

I'm trying to simulate the operation of 74HC194 with Logisim. I found its logic diagram from an NXP datasheet but I'm having some difficulties getting it to work.
The data sheet mentions:
>The synchronous operation of the device is determined by the mode select inputs (S0, S1). In parallel load mode (S0
and S1 HIGH) data appearing on the D0 to D3 inputs, when S0 and S1 are HIGH, is transferred to the Q0 to Q3 outputs.
>When S0 is HIGH and S1 is LOW data is entered serially via DSL and shifted from left to right;
>when S0 is LOW and S1 is HIGH data is entered serially via DSR and shifted from right to left. DSR and DSL allow multistage shift right or shift left data transfers without interfering with parallel load operation.
>If both S0 and S1 are LOW, existing data is retained in a hold mode.

However, if I first set S0 and S1 high and set any of the data inputs high, all outputs are set high after a clock pulse. Pic related, situation after low->high clock transition.

Can anyone spot any errors in my simulation model?