/diy/ - Do It Yourself

Anonymous Wed Oct 25 08:38:34 2023 No.2701273 [View]
File: 74 KB, 1162x704, SS 2023-10-25 at 9.35.25 PM.png [View same] [iqdb] [saucenao] [google]

Here's a power latch circuit I made. I just realised that when the FET is turned off, the op-amp's power rails are both at +BATT, and so it might pull the gate high. With a low enough value pull-down resistor R15 this shouldn't be a problem, but such a resistor means pulling the op-amp's output low via a resistor, which may or may not be bad for it.

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/diy/ - Do It Yourself

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