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>> No.25915735 [View]
File: 568 KB, 1366x1024, euv_cymer_asml_architecture_source.png [View same] [iqdb] [saucenao] [google]
25915735

>>25915602
most chips don't need to be fabricated on cutting edge nodes where EUV is used (think about the billions of random ICs and microcontrollers out there). the cost of building an IC on a cutting edge node where EUV is useful is fucking high: https://semiengineering.com/going-to-gate-all-around-fets/

>At 5nm, it will cost $500 million or more to design a “reasonably complex SoC,” Johnson said. In comparison, it will cost $271 million to design a 7nm SoC, which is about 9 times the cost for a 28nm planar device, according to Gartner.

>Is it a matter of patents or just precision manufacturing?
patents + difficulty in development

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